Server System Architecture, 2002



The ServerWorks HE-SL brings some of the HE features into a chipset for dual processor Pentium III systems. This includes two memory channels for 2-way interleaved operation with 12GB maximum memory and the use of high speed Inter-Module Buses for greatly improved I/O bus bandwidth. The IMB links the north bridge to I/O bridges (CIOB2). Each CIOB2 device can support two 64-bit 66MHz PCI buses. Most HE-SL systems implement only a single CIOB2 with the two 64-bit 66MHz PCI buses, along with the 32-bit 33MHz PCI bus attached the CSB south bridge.

Figure 4. ServerWorks HE-SL chipset.

The ServerWorks HE-SL represents the new trend in server chipset design. The north bridge links directly with the latency critical memory bus. The I/O busses, which are less sensitive to latency, connect via a bridge chip. This allows the north bridge to connect to the I/O bridge chip on high bandwidth busses while conserving pin-count. The extra bridge chip may add 20-30ns latency. However I/O devices generally have much higher latency so the latency introduced by a bridge chip is negligible.

Figure 5, below, shows the layout of an 8-way Pentium III Xeon server based on the Intel ProFusion chipset. The overall system is comprised of five busses: two processor busses, two memory channels, and one I/O bus. The I/O bus supports four peer PCI busses. It is difficult for a single device to connect all the signals for the five busses and two cache coherency (SRAM) boards. The Profusion north bridge is implemented in two separate components. The Memory Access Controller (MAC) links the address signals and the Data Interface Buffer (DIB) links the data signals.

The processors are divided into two separate busses each with up to four processors. The cache coherency filters allows processors on one bus to determine if a particular 32-byte block of memory is in the cache of one of the processors on the other bus. This reduces snoop traffic to the other bus to maintain cache coherency.

Figure 5. 8-way Pentium III Xeon system with Intel Profusion chipset.

The Profusion chipset can address up to 32GB of memory on 32 DIMM sites with capacities from 128MB to 1GB. Each memory channel can support up to 16 DIMM sites, so each channel is expanded into four electrically separated busses. The ProFusion architecture does not use interleaved memory in the same manner as the ServerSet III design. A four-word (4×8 byte) memory request will access one SDRAM DIMM in the standard X-1-1-1 manner. Memory addresses, however, are interleaved across 32 byte (the size of the processor cache line) partitions. Even addresses map to one memory channel, odd addresses map to the other memory channel. In the both cases, the design is intended support higher realizable memory access rates than a single memory channel. 

The PCI busses are connected to an I/O bus by PCI bus expanders (PB64). The I/O bus has a bandwidth of 800MB/sec and supports a maximum of four PB64 devices. Each PB64 can support a 64-bit bus at either 66MHz or 33MHz. Most eight-way servers implement four 64-bit PCI busses, two capable of 66MHz operation, each with 2 slots, and two 33MHz busses, one with four slots, the other with two slots and embedded SCSI. The combined bandwidth of the four PCI busses (1.6GB/sec) is greater than the I/O bus (800MB/sec), but this is should not be an issue. It would take a highly unusual and perhaps contrived circumstance for all busses to be saturated in a cumulative manner. Regardless of the peak sustainable I/O bandwidth, it can be beneficial to employ the highest bandwidth PCI adapters available (64-bit 66MHz) to allow individual actions to complete as quickly as possible and with minimum latency  

Pentium 4 and Xeon Server System

The low end of entry-level servers are generally built on a desktop chipset. The features of a desktop chipset are not necessarily the best match for servers, but almost nothing has lower cost structure than a desktop chipset. Figure 6 below shows the layout of a single processor Pentium 4 system with the Intel 845E chipset. Desktop chipsets used to support dual processor configurations in the Pentium II and Pentium III generations, but this capability was dropped to meet the more stringent electrical requirements for the 400MHz system data bus on Pentium 4 processors. The two major components of the 845E chipset are the Memory Controller Hub (MCH) and the I/O Controller Hub (ICH). The MCH is the north bridge and ICH is the south bridge. The MCH interfaces the low voltage buses (<2V) and the ICH interfaces older high voltage buses (5V and 3.3V).

Figure 6. Intel 845E chipset.

Pentium 4 system data bus is 64-bits wide and operates at either 400MHz or 533MHz for a bandwidth of 3.2GB/sec or 4.2GB/sec. The system data bus is quad-pumped, that is, the data transfer rate is four times the bus clock. The bus clock is actually 100MHz or 133MHz for some of the more recent versions. For marketing reasons, it is less confusing to explain only the data transfer rate. The address rate is the same as the bus clock of 100 or 133MHz. The 845E memory bus is a 64-bit DDR interface (72-bit with ECC) with either 200MHz data transfer rate for a bandwidth of 1.6GB/sec for the 400MHz front-side bus (FSB) or 266MHz, 2.1GB/sec for the 533MHz FSB

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