Server System Architecture, 2002
This article is intended to provide software developers and IT administrators a basis for comparing server systems. The focus is on platforms for Intel processors and Windows NT, 2000 Server operating systems. Server system architectures can change substantially in 2-4 years, so it is important to understand the new capabilities introduced in each succeeding generation.
Computer system architecture generally describes the capabilities and organization of the three key component resources: processors, memory and I/O devices. Each of the three components are typically designed and manufactured with different interfaces. Almost all computer systems employ a core logic chipset to link the disparate processor, memory and I/O interfaces. The processor and chipset essentially determines the system architecture.
There are only a few server chipsets for each of the current processor architectures. A basis for comparing almost all the server systems available can be made by examining each of the chipsets in detail. The general characteristics and direction of chipsets are discussed first. The actual chipsets to be examined are divided by processor family:
1) Pentium III and Pentium III Xeon
2) Pentium 4 and Xeon
3) Itanium II
Many server systems in use today are based on the Pentium III processors. Pentium 4 and Xeon systems will gradually replace the Pentium III systems except for some low power and high-density platforms. The first generation Itanium systems essentially have served as a software development platform. The second generation Itanium system has been announced with imminent availability. It is this generation that is expected to make a more significant impact, so the Itanium 2 systems are examined instead of the first generation Itanium systems.
The Pentium 4 is a new and radically different micro-architecture for the original IA-32 (or X86) instruction set architecture (ISA). Where Pentium Pro, Pentium II and Pentium III were all designed around the same bus protocol, the Pentium 4 has both a new core and bus protocol. This is comparable to the transition from the Pentium to Pentium Pro, where new chipsets designed around a different bus protocol were required. Bus enhancements for the Pentium 4 include a 400MHz data transfer rate on the system bus for a bandwidth of 3.2GB/sec and a complete overhaul of the APIC bus for multiprocessor systems.
The Itanium processor line is an entirely new instruction set architecture as well as unrelated in micro-architecture to the Intel IA-32 processors.
General Chipset Characteristics
Figure 1 below shows a generic chipset. The chipset links a processor bus, a memory bus and an I/O bus. This generic chipset is implemented in two components, a north bridge and a south bridge. The north bridge links the processor and memory buses. The south bridge links one or more I/O buses. The separation of functions allows the north bridge to connect low voltages devices (<2.5V) and the south bridge to connect higher voltages devices (3.3V and 5V). The processor and memory are generally manufactured on a more advanced semiconductor process technology (0.18 and 0.13µm) for performance and cost considerations, which favors lower voltage (2.5V or less) operation. I/O devices tend to stay on a fixed voltage longer, allowing for a larger pool of interoperable adapters. The PCI bus specification allows for either 5V or 3.3V operation, with newer designs favoring the 3.3V only option. The AGP bus, designed specifically as a point-to-point link to the graphics chip that requires greater performance capabilities, has already moved to 1.5V operation and can connect to the north bridge.
Figure 1. Generic chipset.
Some chipsets today integrate graphics functions in the north bridge. This is done for one of two reasons; performance and cost. Integrating the north bridge and graphics chips reduces latency between the processor and the graphics chip, which can improve performance. Consolidating two silicon chips into a single chip can reduce cost. For low complexity devices, the packaging for a chip can cost as much as the silicon itself. The cost of the single integrated chip may be more than the two discrete chips, but the lower packaging cost more than compensates. A performance-oriented design may implement a high-bandwidth memory subsystem. Instead of two separate memory channels, one on the north bridge for main memory and one on the graphics controller, an integrated chipset could have a single high-bandwidth memory subsystem for both main memory and graphics, from which bandwidth can allocated as needed. A low cost implementation might have just a single standard memory channel to save the cost of the graphics memory subsystem. The Intel 815 and 845G are low cost integrated chipset designs. The NVIDIA nForce2 is an example of a performance-oriented chipset with integrated north bridge and graphics.
Future desktop systems may integrate the north bridge into the processor itself. This can increase performance by reducing memory latency with one less step between the processor and memory, and reduce overall system cost. It is important to select the most suitable memory interface for the intended application. Matching a high-end memory interface to a low cost product is not a good choice.
A major goal driving server chipset design is the ability to route as much bandwidth between processor, memory and I/O as possible. Since a single device can have only so many signal pins for a given cost range, the high bandwidth goal requires achieving as high a signaling rate as possible. A shared bus that connects many devices allows a lower signaling rate than a bus that connects fewer devices. This leads to point-to-point signaling rather than a shared bus. Point-to-point designs also benefit from bi-directional signaling, which allows signals to be sent in both directions simultaneously.