Server System Architecture, 2002

Figure 10 below shows the Server Works GC-HE chipset for 4-way Xeon systems. The GC-HE north bridge has a 4-way interleaved DDR memory subsystem and can support three CIOB-X for a combined bandwidth of 5GB/sec, even though each IMB bus can signal at 3.2GB/sec. This supports the claim that the full I/O bandwidth is not entirely required.

Figure 10. ServerWorks GC-HE 4-way Xeon system.

There is also the IBM XA-32 chipset for the Xeon processor that supports 4 Xeon processors in one node and allows four nodes to be linked together. The XA-32 north bridge has a 32MB SRAM cache. This extra cache can provide 15-20% performance increase. The size of the SRAM cache leads one to ask whether the role of SRAM in memory systems should be reconsidered.

All of the Pentium 4 and Xeon chipsets targeted for server system employ DDR memory. Some Intel desktop chipsets support RDRAM, but no server systems are designed with RDRAM. The ability to configure a large amount of memory economically is important for server systems. A major advantage of RDRAM is the ability to support high-bandwidth in a relatively small memory configuration (128M), which is not important in server systems. The disadvantage of RDRAM is that cost per chip is higher than that of DDR. This may not be a major liability in a high-end desktop system with only 256MB of memory, but is for a server system with multi-GB memory configurations. 

The chipsets designed specifically for server systems all support PCI-X up to 133MHz. Technically the ServerWorks GC-LE chipset has more I/O bandwidth than the Intel E7500, but so far there are no clear demonstrations with actual applications that can need multi-gigabyte/sec I/O bandwidth. It is not unheard of for new hardware technologies to enable very large boosts in bandwidth. However, it may take some time for the operating system and applications to be properly tuned to take full advantage of the new bandwidth.

Itanium 2 Chipsets

Figure 11 below shows the Intel E8870 chipset for 2-way and 4-way Itanium 2 systems. The E8870 chipset shown has three major components; a Scalable Node Controller (SNC), four DDR Memory Hubs (DMH), and one Server Input/Output Hub (SIOH). Components not shown include an ICH for legacy and low-bandwidth devices.

Figure 11. Intel E8870 chipset.

A component to be released at a later date is the Scalability Port Switch (SPS) which can link four SNC nodes together into 8 or 16-way systems, depending on whether each node is configured with 2 or 4 processors.

The Itanium 2 systems data bus is 128-bits wide and operates at 400MHz for a data bandwidth of 6.4GB/sec. The data bus is double-pumped, where two data words are transferred each clock-cycle. The bus clock is 200MHz as is the address bus. This is actually better than the 400MHz Pentium 4 quad-pumped data bus because the Itanium 2 address bus operates at 200MHz versus 100MHz.


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