The E8870 SNC memory interface is comprised of four 1.6GB/sec RDRAM interfaces for a total bandwidth of 6.4GB/sec. When it became apparent that RDRAM would not be the memory of choice for server systems, the DMH was added to support DDR memory. The SNC has two 3.2GB/sec Scalability Port (SP) interfaces that can connect to the SIOH. The SP interface is a very high-speed point-to-point protocol similar in concept to the ServerWorks IMB. Both are designed to route as much bandwidth per pin as possible. The SP interface will also be able connect to the SPS when it becomes available. The SIOH has two SP interfaces for the SNC connection, four HI 2.0 interfaces that connect to P64H2 devices (same as on the Intel E7500), and one HI 1.5 interface that connects to an ICH.
Figure 12 below shows the HP zx1 chipset for 2-way Itanium 2 systems. The two major components of the zx1 in a 2-way configuration are the Memory and I/O controller (MIO) and seven Input/Output Adapters (IOA).
Figure 12. HP ZX1 chipset for 2-way Itanium 2 system.
Figure 13 below shows the HP zx1 chipset for a 4-way Itanium 2 system. The 4-way configuration has two Scalable Memory Extenders, each implemented on six chips, in addition to the MIO and IOA.
The zx1 MIO implements two 128-bit DDR memory interfaces. The MIO memory interface can operate at 400MHz for a bandwidth of 6.4GB/sec per interface. In the 2-way configuration, the MIO memory interface operates asynchronously from the system bus at 266MHz for a bandwidth of 4.256GB/sec. In the 4-way configuration, the MIO memory interface operates at 400MHz. DDR memory is not currently available at 400MHz, so the SME splits the 128-bit 400MHz interface into four separate 128-bit DDR interfaces operating at 200MHz.
Figure 13. HP zx1 chipset for 4-way Itanium 2 system.
HP touts the zx1 chipset as having exceptional memory latency, that is, lower than expected memory latency. Memory latency is often an under appreciated aspect of system performance, and can be more important than bandwidth in some applications. It is not clear whether HP reduced the latency by some unknown technique or by clever choice of design and components. Server systems generally prefer to support very large memory configurations. This includes using registered DIMMs in order to support 4 DIMMs on one bus. A registered DIMM adds one clock in latency compared to an unbuffered DIMM, which can only supports 2-3 DIMMs per bus. The zx1 implements two 128-bit memory interfaces. Each memory interface is comprised of two 64-bit (72 with ECC) data busses. The doublewide memory allows large memory configurations to be reached without the use of registered DIMMs. Each DDR bus supports 3 DIMMs for a total of 12 DIMMs. The zx1 also uses the lower latency CL2 DDR modules instead of the more common CL2.5 used in other server systems.
Each zx1 IOA can transfer data to the MIO at 1GB/sec, but most are configured for 0.5GB/sec operation. The combined I/O bandwidth to the MIO is 4GB/sec. The IOA can support either 1 PCI-X 133MHz slot or 2 PCI-X 66MHz slots. The 2-way system has 7 IOA and the 4-way system has 8 IOA. Two or three of the IOA are configured with embedded devices and other IOA have PCI-X slots.
Server System Architecture Summary
The server system architecture is shown to be largely determined by the processor and chipset. The significant differences between desktop and dedicated server chipsets can include interleaved memory, multiple high-bandwidth I/O busses and other reliability features not covered. Interleaved memory is frequently marketed as having 2X or 4X the memory bandwidth of other systems, but this is misinterpretation (also known as a marketing interpretation) of the true benefit of interleaved memory.
Most of the later Pentium III generation chipsets support SDRAM memory and 64-bit 66MHz PCI I/O. The newer Pentium 4 and Itanium 2 generation chipsets support DDR memory and 64-bit 133MHz PCI-X I/O. The high I/O bandwidth even with the Pentium III generation of chipsets warrants rethinking of I/O configuration strategy. Any rules that were developed for the old 133MB/sec PCI busses may be no longer entirely correct. New configuration strategies should be developed to best employ the bandwidth now available.
Published with the express written permission of the author. Copyright 2002 by the author
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